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Latch-up problem in cmos – vlsi design – buzztech
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Earlier Is Better In Latch-Up Detection

Analog IC co-design for latch-up compliance - EDN Asia

Latch-Up Problem in CMOS – VLSI Design – Buzztech

PPT - Latch-UP PowerPoint Presentation, free download - ID:5779057
What is Latch-Up and How to Test It - AnySilicon

Figure 1 from High Holding Current SCRs (HHI-SCR) for ESD protection
![[SOLVED] - How to use SCR as a Latch? | Forum for Electronics](https://i2.wp.com/www.edaboard.com/data/attachments/39/39550-a6a39de3374b67aa1344936e0a08b18d.jpg)
[SOLVED] - How to use SCR as a Latch? | Forum for Electronics
Latchup and its prevention in CMOS devices